The present invention relates to stacked CMOS integrated circuits, i.e., to integrated circuits containing both N-channel and P-channel insulated gate field effect devices.
It is widely recognized in the art that it would be highly desirable to achieve practical stacked CMOS integrated circuits, i.e., circuits where a single gate at a single location is capacitatively coupled to control both N-channel and P-channel devices. It is usually assumed that the N-channel devices would be formed in the substrate and the P-channel devices would be formed in polysilicon, although this is not strictly necessary.
Stacked CMOS has the potential to provide extremely dense integrated circuits, and especially to provide extremely dense memory circuits. However, known methods for fabrication of stacked CMOS structures do not permit the overlayed device to be self-aligned. That is, the mask which is used to pattern the channel region of the overlayed polysilicon is applied in a separate masking step from the patterning of the gate which must address this channel. This means that small geometry devices become unfeasible, since misalignment between the gate and channel region would introduce a disastrous spread in device characteristics.
A stacked CMOS structure is described by S. Malhi in U.S. application No. 505,155, filed June 17, 1983 and assigned to the assignee of the present application. The method described therein is not fully self-aligned, so that misalignment can occur.
Thus it is an object of the present invention to provide a method for fabricating stacked CMOS integrated circuits wherein an overlayed polysilicon device has a channel region which is fully self-aligned to a gate electrode beneath the channel region.
Therefore, according to the present invention, a doped layer is formed over an existing gate region, and planarized. This layer is then anisotropically etched until an upper surface of the gate region is exposed. Regions of the doped layer will remain over portions of the integrated circuit which are lower than the top surface of the gate region. A gate oxide is formed over the gate region, followed by a layer of polycrystalline silicon. Heating of the integrated circuit in an inert ambient causes dopant to diffuse from the doped regions into the polycrystalline silicon, thereby forming heavily doped source and drain regions within the polycrystalline silicon and defining a less heavily doped channel region directly above the gate region.
The novel features which characterize the present invention are defined by the appended claims. The foregoing and other objects and advantages of the present invention will hereinafter appear, and for purposes of illustration, but not of limitation, a preferred embodiment is described in the accompanying drawings.